This application claims the benefit of Korean Patent Application No. 2001-12335, filed on Mar. 9, 2001, under 35 U.S.C. xc2xa7119, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a memory device, and more particularly, to an embedded memory and a method of arranging fuses thereof.
2. Description of Related Art
Typically, compiled memories have memory cell arrays of small capacity. Such a compiled memory is packaged along with other logic and functional blocks. The compiled memory is connected to other logic, and function blocks perform a specific function.
An integrated circuit (IC) containing the compiled memory, the other logic and the function blocks is referred to as an application specific integrated circuit (ASIC). The embedded memory is one in which the compiled memory is embedded in the ASIC.
The compiled memory is designed by programming a memory having a memory cell array of a specific capacity. Due to its small capacity, the compiled memory does not include a redundancy circuit and thus is not repaired even though a defect occurs.
However, as the functions of the ASIC become diverse and thus data to be process increases, the compiled memory of large capacity becomes increasingly required. Hence, the compiled memory of relative large capacity requires a redundancy circuit.
A redundancy circuit for use in the compiled memory is configured in such a way that fuses are arranged gathered at one position in order to form a fuse box. However, the compiled memory having the redundancy circuit in the form of a fuse box is inefficient in layout, and suffers from delayed signal transmission because signal lines that lie over the compiled memory should not overlap over the fuse box and thus are more lengthy than they would otherwise need to be.
To overcome the problems described above, preferred the present invention provides an embedded memory and a method of arranging fuses thereof that can provide an efficient layout and improved signal transmission.
The present invention is directed to an embedded memory. In a first aspect, the embedded memory includes a memory cell array, a predetermined number of first function circuits for controlling input and output of data of the memory cell array, and at least one second function circuit having a predetermined number of fuses, wherein the predetermined number of fuses are arranged separately from each other in at least one of the predetermined number of the first function circuits.
The present invention further provides a method of arranging fuses of an embedded memory having a memory cell array, a predetermined number of first function circuits for controlling input and output of data of the memory cell array, and at least one second function circuit having a predetermined number of fuses. The method includes arranging the predetermined number of fuses separately from each other in at least one of the predetermined number of first function circuits.
In another aspect, the invention is directed to a circuit with an embedded memory. The circuit includes signal lines lying over the embedded memory. A redundancy circuit has a plurality of fuse portions, each of the fuse portions being separately arranged between the two adjacent signal lines.
In another aspect, the invention is directed to an embedded memory. The memory includes a redundancy circuit having a plurality of fuse portions, the fuse portions being arranged independently from each other.
Since the embedded memory has the fuses arranged separately from each other, an efficient layout can be achieved, and a signal transmission rate can be improved.